
17
LTC1404
1404fa
Figure 14. CLK to DOUT Delay
APPLICATIONS INFORMATION
WU
U
CLK
CONV
INTERNAL
S/H STATUS
DOUT
t7
t3
12
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
t2
t6
t4
t5
t8
tACQ
SAMPLE
HOLD
REFRDY BIT + 12-BIT DATA WORD
Hi-Z
tCONV
tSAMPLE
1404 F13
REFRDY
D11
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D10
REFRDY
Figure 13. ADC Digital Timing Diagram
t10
t8
VIH
VOH
VOL
DOUT
CLK
t9
VIH
90%
10%
DOUT
CLK
1404 F14